#ifndef __CSP_SCU_H__
#define __CSP_SCU_H__

//#include "AC33Mx128.h"

typedef struct {

	CSP_REGISTER_T		CIDR;				// addr = 0x4000_0000, RO
	CSP_REGISTER_T		SMR;				// addr = 0x4000_0004, R/W
	CSP_REGISTER_T		SRCR;				// addr = 0x4000_0008, R/W
	CSP_REGISTER_T		res0C;				// addr = 0x4000_000C
	
	CSP_REGISTER_T		WUER;				// addr = 0x4000_0010, R/W
	CSP_REGISTER_T		WUSR;				// addr = 0x4000_0014, R/W
	CSP_REGISTER_T		RSER;				// addr = 0x4000_0018, R/W
	CSP_REGISTER_T		RSSR;				// addr = 0x4000_001C, R/W 

	CSP_REGISTER_T		PRER1;				// addr = 0x4000_0020, R/W
	CSP_REGISTER_T		PRER2;				// addr = 0x4000_0024, R/W
	CSP_REGISTER_T		PER1;				// addr = 0x4000_0028, R/W
	CSP_REGISTER_T		PER2;				// addr = 0x4000_002C, R/W 

	CSP_REGISTER_T		PCER1;				// addr = 0x4000_0030, R/W
	CSP_REGISTER_T		PCER2;				// addr = 0x4000_0034, R/W
	CSP_REGISTER_T		res38;				// addr = 0x4000_0038
	CSP_REGISTER_T		res3C;				// addr = 0x4000_003C 	

	CSP_REGISTER_T		CSCR;				// addr = 0x4000_0040, R/W
	CSP_REGISTER_T		SCCR;				// addr = 0x4000_0044, R/W
	CSP_REGISTER_T		CMR;				// addr = 0x4000_0048, R/W
	CSP_REGISTER_T		NMIR;				// addr = 0x4000_004C, R/W 

	CSP_REGISTER_T		COR;				// addr = 0x4000_0050, R/W
	CSP_REGISTER_T		res54;				// addr = 0x4000_0054
	CSP_REGISTER_T		res58;				// addr = 0x4000_0058
	CSP_REGISTER_T		TRIMENT;			// addr = 0x4000_005C, R/W 	

	CSP_REGISTER_T		PLLCON;				// addr = 0x4000_0060, R/W
	CSP_REGISTER_T		VDCCON;				// addr = 0x4000_0064, R/W
	CSP_REGISTER_T		BODCON;				// addr = 0x4000_0068, R/W
	CSP_REGISTER_T		IOSCTRIM;			// addr = 0x4000_006C, R/W 

	CSP_REGISTER_T		OPA0TRIM;			// addr = 0x4000_0070, R/W
	CSP_REGISTER_T		OPA1TRIM;			// addr = 0x4000_0074, R/W
	CSP_REGISTER_T		OPA2TRIM;			// addr = 0x4000_0078, R/W
	CSP_REGISTER_T		OPA3TRIM;			// addr = 0x4000_007C, R/W 	

	CSP_REGISTER_T		EOSCR;				// addr = 0x4000_0080, R/W
	CSP_REGISTER_T		EMODR;				// addr = 0x4000_0084, R/W
	CSP_REGISTER_T		res88;				// addr = 0x4000_0088
	CSP_REGISTER_T		res8C;				// addr = 0x4000_008C

	CSP_REGISTER_T		MCCR1;				// addr = 0x4000_0090, R/W
	CSP_REGISTER_T		MCCR2;				// addr = 0x4000_0094, R/W
	CSP_REGISTER_T		MCCR3;				// addr = 0x4000_0098, R/W
	CSP_REGISTER_T		MCCR4;				// addr = 0x4000_009C, R/W
	
	CSP_REGISTER_T		MCCR5;				// addr = 0x4000_00A0, R/W
	CSP_REGISTER_T		MCCR6;				// addr = 0x4000_00A4, R/W
	
} CSP_SCU_T;


// SCU 
extern CSP_SCU_T			* const 		SCU; 	

//==========================================================================
// 	CIDR 
//		
//
//==========================================================================


//==========================================================================
// 	SMR
//		
//
//==========================================================================

//==========================================================================
// 	SCR 
//		
//
//==========================================================================



//==========================================================================
// 	WUER
//
//				@ address = 0x4000_0010
//
//
//==========================================================================
#define WUER_GPIODWUE					(0x0001<<11)
#define WUER_GPIOBWUE					(0x0001<<9)
#define WUER_GPIOAWUE					(0x0001<<8)

#define WUER_WDTWUE						(0x0001<<1)
#define WUER_BODWUE						(0x0001<<0)

//==========================================================================
// 	RSER
//
//				@ address = 0x4000_0018
//
//
//==========================================================================
#define RSER_PINRST						(0x0001<<6)
#define RSER_CORERST					(0x0001<<5)
#define RSER_SWRST						(0x0001<<4)
#define RSER_WDTRST						(0x0001<<3)
#define RSER_MCKFRST					(0x0001<<2)
#define RSER_XFRST						(0x0001<<1)
#define RSER_LVDRST						(0x0001<<0)


//==========================================================================
// 	PRER1
//		
//
//==========================================================================
#define PRER1_TIMER9					(0x0001<<25)
#define PRER1_TIMER8					(0x0001<<24)

#define PRER1_TIMER3					(0x0001<<19)
#define PRER1_TIMER2					(0x0001<<18)
#define PRER1_TIMER1					(0x0001<<17)
#define PRER1_TIMER0					(0x0001<<16)

#define PRER1_GPIOD						(0x0001<<11)
#define PRER1_GPIOC						(0x0001<<10)
#define PRER1_GPIOB						(0x0001<<9)
#define PRER1_GPIOA						(0x0001<<8)

#define PRER1_DMA						(0x0001<<4)

#define PRER1_PCU						(0x0001<<3)
#define PRER1_WDT						(0x0001<<2)
#define PRER1_FMC						(0x0001<<1)
#define PRER1_SCU						(0x0001<<0)

#define PRER1_ALL						(0xFFFFFFFF)


//==========================================================================
// 	PRER2
//		
//
//==========================================================================
#define PRER2_AFE						(0x0001<<23)

#define PRER2_ADC2						(0x0001<<22)
#define PRER2_ADC1						(0x0001<<21)
#define PRER2_ADC0						(0x0001<<20)

#define PRER2_MPWM1						(0x0001<<17)
#define PRER2_MPWM0						(0x0001<<16)

#define PRER2_UART3						(0x0001<<11)
#define PRER2_UART2						(0x0001<<10)
#define PRER2_UART1						(0x0001<<9)
#define PRER2_UART0						(0x0001<<8)

#define PRER2_I2C1						(0x0001<<5)
#define PRER2_I2C0						(0x0001<<4)

#define PRER2_SPI1						(0x0001<<1)
#define PRER2_SPI0						(0x0001<<0)

#define PRER2_ALL						(0xFFFFFFFF)


//==========================================================================
// 	PER1
//		
//
//==========================================================================
#define PER1_TIMER9						(0x0001<<25)
#define PER1_TIMER8						(0x0001<<24)

#define PER1_TIMER3						(0x0001<<19)
#define PER1_TIMER2						(0x0001<<18)
#define PER1_TIMER1						(0x0001<<17)
#define PER1_TIMER0						(0x0001<<16)

#define PER1_GPIOD						(0x0001<<11)
#define PER1_GPIOC						(0x0001<<10)
#define PER1_GPIOB						(0x0001<<9)
#define PER1_GPIOA						(0x0001<<8)

#define PER1_DMA						(0x0001<<4)

#define PER1_ALL						(0xFFFFFFFF)


//==========================================================================
// 	PER2
//		
//
//==========================================================================
#define PER2_AFE						(0x0001<<23)

#define PER2_ADC2						(0x0001<<22)
#define PER2_ADC1						(0x0001<<21)
#define PER2_ADC0						(0x0001<<20)

#define PER2_MPWM1						(0x0001<<17)
#define PER2_MPWM0						(0x0001<<16)

#define PER2_UART3						(0x0001<<11)
#define PER2_UART2						(0x0001<<10)
#define PER2_UART1						(0x0001<<9)
#define PER2_UART0						(0x0001<<8)

#define PER2_I2C1						(0x0001<<5)
#define PER2_I2C0						(0x0001<<4)

#define PER2_SPI1						(0x0001<<1)
#define PER2_SPI0						(0x0001<<0)

#define PER2_ALL						(0xFFFFFFFF)


//==========================================================================
// 	PCER1
//		
//
//==========================================================================
#define PCER1_TIMER9					(0x0001<<25)
#define PCER1_TIMER8					(0x0001<<24)

#define PCER1_TIMER3					(0x0001<<19)
#define PCER1_TIMER2					(0x0001<<18)
#define PCER1_TIMER1					(0x0001<<17)
#define PCER1_TIMER0					(0x0001<<16)

#define PCER1_GPIOD						(0x0001<<11)
#define PCER1_GPIOC						(0x0001<<10)
#define PCER1_GPIOB						(0x0001<<9)
#define PCER1_GPIOA						(0x0001<<8)

#define PCER1_DMA						(0x0001<<4)

#define PCER1_ALL						(0xFFFFFFFF)


//==========================================================================
// 	PCER2
//		
//
//==========================================================================
#define PCER2_AFE						(0x0001<<23)

#define PCER2_ADC2						(0x0001<<22)
#define PCER2_ADC1						(0x0001<<21)
#define PCER2_ADC0						(0x0001<<20)

#define PCER2_MPWM1						(0x0001<<17)
#define PCER2_MPWM0						(0x0001<<16)

#define PCER2_UART3						(0x0001<<10)
#define PCER2_UART2						(0x0001<<10)
#define PCER2_UART1						(0x0001<<9)
#define PCER2_UART0						(0x0001<<8)

#define PCER2_I2C1						(0x0001<<5)
#define PCER2_I2C0						(0x0001<<4)

#define PCER2_SPI1						(0x0001<<1)
#define PCER2_SPI0						(0x0001<<0)

#define PCER2_ALL						(0xFFFFFFFF)



//==========================================================================
// 	CSCR
//		
//				@ address = 0x4000_0040
//
//==========================================================================
#define CSCR_RINGOSCCON_STOP			(0x0000<<4)
#define CSCR_RINGOSCCON_ENABLE			(0x0002<<4)
#define CSCR_RINGOSCCON_ENABLE_DIV_BY2	(0x0003<<4)

#define CSCR_IOSCCON_STOP				(0x0000<<2)
#define CSCR_IOSCCON_ENABLE				(0x0002<<2)
#define CSCR_IOSCCON_ENABLE_DIV_BY2		(0x0003<<2)

#define CSCR_EOSCON_STOP				(0x0000<<0)
#define CSCR_EOSCON_ENABLE				(0x0002<<0)
#define CSCR_EOSCON_ENABLE_DIV_BY2		(0x0003<<0)


//==========================================================================
// 	SCCR
//		
//				@ address = 0x4000_0044
//
//==========================================================================
#define SCCR_FINSEL_IOSC				(0x0000<<2)
#define SCCR_FINSEL_MOSC				(0x0001<<2)

#define SCCR_MCLKSEL_INTERNAL_RINGOSC	(0x0000<<0)
//#define SCCR_MCLKSEL_SUB_OSCXTAL		(0x0001<<0)
#define SCCR_MCLKSEL_PLL_BYPASS			(0x0002<<0)
#define SCCR_MCLKSEL_PLL				(0x0003<<0)
#define SCCR_MCLKSEL_MASK				(0x0003<<0)

#define SCCR_MASK						(0x0007<<0)

#define IOSC20M_INPUT					(SCCR_FINSEL_IOSC)
#define XTAL8M_INPUT					(SCCR_FINSEL_MOSC)




//==========================================================================
// 	CMR
//		
//				@ address = 0x4000_0048
//
//==========================================================================
#define CMR_MCLKREC						(0x0001<<15)

#define CMR_MCLKMNT						(0x0001<<7)
#define CMR_MCLKIE						(0x0001<<6)
#define CMR_MCLKFAIL					(0x0001<<5)
#define CMR_MCLKSTS						(0x0001<<4)

#define CMR_EOSCMNT						(0x0001<<3)
#define CMR_EOSCIE						(0x0001<<2)
#define CMR_EOSCFAIL					(0x0001<<1)
#define CMR_EOSCSTS						(0x0001<<0)
#define CMR_EOSC_MASK					(0x000F<<0)


//==========================================================================
// 	COR
//		
//				@ address = 0x4000_0050
//
//==========================================================================
#define COR_CLKOEN						(0x0001<<4)

#define COR_CLKODIV_MASK				(0x000F<<0)

#define COR_MASK						(0x001F<<0)


//==========================================================================
// 	PLLCON
//		
//				@ address = 0x4000_0060
//
//==========================================================================
#define PLLCON_PLLRSTB					(0x0001<<15)
#define PLLCON_PLLRSTB_ASSERT			(0x0000<<15)
#define PLLCON_PLLRSTB_LIFT				(0x0001<<15)

#define PLLCON_PLLEN					(0x0001<<14)

#define PLLCON_BYPASS					(0x0001<<13)
#define PLLCON_BYPASS_ENABLE			(0x0000<<13)
#define PLLCON_BYPASS_DISABLE			(0x0001<<13)


#define PLLCON_LOCKSTS					(0x0001<<12)

#define PLLCON_PREDIV_DIV_BY_1			(0x0000<<8)
#define PLLCON_PREDIV_DIV_BY_2			(0x0001<<8)

#define PLLCON_FBCTRL_6					(0x0000<<4)
#define PLLCON_FBCTRL_8					(0x0001<<4)
#define PLLCON_FBCTRL_10				(0x0002<<4)
#define PLLCON_FBCTRL_12				(0x0003<<4)

#define PLLCON_FBCTRL_16				(0x0004<<4)
#define PLLCON_FBCTRL_18				(0x0005<<4)
#define PLLCON_FBCTRL_20				(0x0006<<4)
#define PLLCON_FBCTRL_26				(0x0007<<4)

#define PLLCON_FBCTRL_32				(0x0008<<4)
#define PLLCON_FBCTRL_36				(0x0009<<4)
#define PLLCON_FBCTRL_40				(0x000A<<4)
#define PLLCON_FBCTRL_64				(0x000B<<4)

#define PLLCON_POSTDIV_MASK				(0x0007<<0)

#define PLLCON_SETTING_MASK				(0x01FF<<0)


//==========================================================================
// 	BODCON
//		
//				@ address = 0x4000_0068
//
//==========================================================================
#define BODCON_SELEN					(0x0001<<15)

#define BODCON_BODSEL_1_80V				(0x0000<<8)
#define BODCON_BODSEL_2_20V				(0x0001<<8)
#define BODCON_BODSEL_2_70V				(0x0002<<8)
#define BODCON_BODSEL_4_30V				(0x0003<<8)

#define BODCON_BODEN_DISABLE			(0x0000<<0)
#define BODCON_BODEN_ENABLE				(0x0001<<0)


//==========================================================================
// 	MCCR1
//		
//				@ address = 0x4000_0090
//
//==========================================================================
#define MCCR1_TRCPOL					(0x0001UL<<31)

#define MCCR1_TRCSEL_RINGOSC1M			(0x0000UL<<24)
#define MCCR1_TRCSEL_SUB_XTAL			(0x0003UL<<24)
#define MCCR1_TRCSEL_MCLK				(0x0004UL<<24)
#define MCCR1_TRCSEL_IOSC20M			(0x0005UL<<24)
#define MCCR1_TRCSEL_MAIN_XTAL			(0x0006UL<<24)
#define MCCR1_TRCSEL_PLL				(0x0007UL<<24)

#define MCCR1_TRACEDIV_MASK				(0x00FFUL<<16)

#define MCCR1_STCSEL_RINGOSC1M			(0x0000UL<<8)
#define MCCR1_STCSEL_SUB_XTAL			(0x0003UL<<8)
#define MCCR1_STCSEL_MCLK				(0x0004UL<<8)
#define MCCR1_STCSEL_IOSC20M			(0x0005UL<<8)
#define MCCR1_STCSEL_MAIN_XTAL			(0x0006UL<<8)
#define MCCR1_STCSEL_PLL				(0x0007UL<<8)

#define MCCR1_STDIV_MASK				(0x0000UL<<0)


//==========================================================================
// 	MCCR2
//		
//				@ address = 0x4000_0094
//
//==========================================================================
#define MCCR2_PWM1CSEL_RINGOSC1M		(0x0000UL<<24)
#define MCCR2_PWM1CSEL_SUB_XTAL			(0x0003UL<<24)
#define MCCR2_PWM1CSEL_MCLK				(0x0004UL<<24)
#define MCCR2_PWM1CSEL_IOSC20M			(0x0005UL<<24)
#define MCCR2_PWM1CSEL_MAIN_XTAL		(0x0006UL<<24)
#define MCCR2_PWM1CSEL_PLL				(0x0007UL<<24)

#define MCCR2_PWM1DIV_MASK				(0x00FFUL<<16)

#define MCCR2_PWM0CSEL_RINGOSC1M		(0x0000UL<< 8)
#define MCCR2_PWM0CSEL_SUB_XTAL			(0x0003UL<< 8)
#define MCCR2_PWM0CSEL_MCLK				(0x0004UL<< 8)
#define MCCR2_PWM0CSEL_IOSC20M			(0x0005UL<< 8)
#define MCCR2_PWM0CSEL_MAIN_XTAL		(0x0006UL<< 8)
#define MCCR2_PWM0CSEL_PLL				(0x0007UL<< 8)

#define MCCR0_PWM0DIV_MASK				(0x00FFUL<< 0)


//==========================================================================
// 	MCCR3
//		
//				@ address = 0x4000_0098
//
//==========================================================================
#define MCCR3_WDTCSEL_RINGOSC			(0x0000<<8)
#define MCCR3_WDTCSEL_SUBXTAL			(0x0003<<8)
#define MCCR3_WDTCSEL_MCLK				(0x0004<<8)
#define MCCR3_WDTCSEL_INTOSC20M			(0x0005<<8)
#define MCCR3_WDTCSEL_EXTOSC			(0x0006<<8)
#define MCCR3_WDTCSEL_PLL				(0x0007<<8)

#define MCCR3_WDTCSEL_MASK				(0x0007<<8)

#define MCCR3_WDTDIV_VAL(n)				(((n)&0xFF)<<0)
#define MCCR3_WDTDIV_MASK				(0x00FF<<0)


//==========================================================================
// 
//		M A C R O S
//
//==========================================================================
#define CSP_SCU_GET_CIDR(scu)					((scu)->CIDR)
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_SMR(scu)					((scu)->SMR)
#define CSP_SCU_SET_SMR(scu, val)				((scu)->SMR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_SCR(scu)					((scu)->SCR)
#define CSP_SCU_SET_SCR(scu, val)				((scu)->SCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_WUER(scu)					((scu)->WUER)
#define CSP_SCU_SET_WUER(scu, val)				((scu)->WUER = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_WUSR(scu)					((scu)->WUSR)
#define CSP_SCU_SET_WUSR(scu, val)				((scu)->WUSR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_RSER(scu)					((scu)->RSER)
#define CSP_SCU_SET_RSER(scu, val)				((scu)->RSER = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_RSSR(scu)					((scu)->RSSR)
#define CSP_SCU_SET_RSSR(scu, val)				((scu)->RSSR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_PRER1(scu)					((scu)->PRER1)
#define CSP_SCU_SET_PRER1(scu, val)				((scu)->PRER1 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_PRER2(scu)					((scu)->PRER2)
#define CSP_SCU_SET_PRER2(scu, val)				((scu)->PRER2 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_PER1(scu)					((scu)->PER1)
#define CSP_SCU_SET_PER1(scu, val)				((scu)->PER1 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_PER2(scu)					((scu)->PER2)
#define CSP_SCU_SET_PER2(scu, val)				((scu)->PER2 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_PCER1(scu)					((scu)->PCER1)
#define CSP_SCU_SET_PCER1(scu, val)				((scu)->PCER1 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_PCER2(scu)					((scu)->PCER2)
#define CSP_SCU_SET_PCER2(scu, val)				((scu)->PCER2 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_CSCR(scu)					((scu)->CSCR)
#define CSP_SCU_SET_CSCR(scu, val)				((scu)->CSCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_SCCR(scu)					((scu)->SCCR)
#define CSP_SCU_SET_SCCR(scu, val)				((scu)->SCCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_CMR(scu)					((scu)->CMR)
#define CSP_SCU_SET_CMR(scu, val)				((scu)->CMR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_NMIR(scu)					((scu)->NMIR)
#define CSP_SCU_SET_NMIR(scu, val)				((scu)->NMIR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_COR(scu)					((scu)->COR)
#define CSP_SCU_SET_COR(scu, val)				((scu)->COR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_TRIMENT(scu)				((scu)->TRIMENT)
#define CSP_SCU_SET_TRIMENT(scu, val)			((scu)->TRIMENT = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_PLLCON(scu)					((scu)->PLLCON)
#define CSP_SCU_SET_PLLCON(scu, val)			((scu)->PLLCON = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_VDCCON(scu)					((scu)->VDCCON)
#define CSP_SCU_SET_VDCCON(scu, val)			((scu)->VDCCON = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_BODCON(scu)					((scu)->BODCON)
#define CSP_SCU_SET_BODCON(scu, val)			((scu)->BODCON = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_IOSCTRIM(scu)				((scu)->IOSCTRIM)
#define CSP_SCU_SET_IOSCTRIM(scu, val)			((scu)->IOSCTRIM = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_OPA0TRIM(scu)				((scu)->OPA0TRIM)
#define CSP_SCU_SET_OPA0TRIM(scu, val)			((scu)->OPA0TRIM = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_OPA1TRIM(scu)				((scu)->OPA1TRIM)
#define CSP_SCU_SET_OPA1TRIM(scu, val)			((scu)->OPA1TRIM = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_OPA2TRIM(scu)				((scu)->OPA2TRIM)
#define CSP_SCU_SET_OPA2TRIM(scu, val)			((scu)->OPA2TRIM = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_OPA3TRIM(scu)				((scu)->OPA3TRIM)
#define CSP_SCU_SET_OPA3TRIM(scu, val)			((scu)->OPA3TRIM = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_EOSCR(scu)					((scu)->EOSCR)
#define CSP_SCU_SET_EOSCR(scu, val)				((scu)->EOSCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_EMODR(scu)					((scu)->EMODR)
#define CSP_SCU_SET_EMODR(scu, val)				((scu)->EMODR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_MCCR1(scu)					((scu)->MCCR1)
#define CSP_SCU_SET_MCCR1(scu, val)				((scu)->MCCR1 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_MCCR2(scu)					((scu)->MCCR2)
#define CSP_SCU_SET_MCCR2(scu, val)				((scu)->MCCR2 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_MCCR3(scu)					((scu)->MCCR3)
#define CSP_SCU_SET_MCCR3(scu, val)				((scu)->MCCR3 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_MCCR4(scu)					((scu)->MCCR4)
#define CSP_SCU_SET_MCCR4(scu, val)				((scu)->MCCR4 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_MCCR5(scu)					((scu)->MCCR5)
#define CSP_SCU_SET_MCCR5(scu, val)				((scu)->MCCR5 = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SCU_GET_MCCR6(scu)					((scu)->MCCR6)
#define CSP_SCU_SET_MCCR6(scu, val)				((scu)->MCCR6 = (val))
//-----------------------------------------------------------------------------------------


//==========================================================================
// 
//		F U N C T I O N    D E C L A R A T I O N S 
//
//==========================================================================
void CSP_SCU_PLLEnable (CSP_SCU_T * const scu, UINT32 pll_input, UINT32 prediv, UINT32 fbctrl, UINT32 postdiv); 




#endif 

